ZTE selects Infineon Technologies to enable Resilient Packet Ring architectures in China

February 26, 2004 Munich, Germany -- ZTE Corp., the second largest supplier of voice and data systems in China, has selected Infineon Technologies as a strategic partner to deliver Resilient Packet Ring (RPR) solutions to its carrier customers. ZTE will use the Infineon Frea Packet-over-SONET (PoS) Framer/RPR Media Access Controller (MAC) integrated circuit (IC) in its metropolitan area network (MAN) and wide area network (WAN) equipment.

RPR technology combines the low cost and simplicity of packet-based networking with the reliability and resiliency of telecom networks. RPR is a Layer Two MAC technology that integrates efficient bandwidth management support and packet services. With Infineon s RPR solution, ZTE can offer service providers the ability to create scalable networks that transport voice and data traffic efficiently while lowering both capital expenses and on-going operational expenses.

"RPR is growing at a phenomenal rate," reports Michael Howard, principal analyst ofInfonetics Research. "The technology has achieved wide acceptance within the industry, and carriers worldwide are already deploying or plan to deploy the technology. Since Asia is a hotspot for metro Ethernet and optical equipment, and 63% of North American and European carriers are planning to offer Ethernet over RPR in the next few years, we expect RPR revenue to grow over 200% by 2007," he asserts.

"The Infineon RPR solution has one of the highest degrees of integration available today," adds Rong Liu, director of networking product division, ZTE. "Infineon s technology is helping ZTE address customer demands for deployable RPR equipment today while meeting technology requirements for reduced power consumption, board design complexity and space, software development, and overall system cost."

The single-chip Frea IC integrates functions previously requiring a minimum of four separate components. The Frea chip integrates the PoS framer, the RPR MAC, and the XAUI SerDes (serializer/deserializer) functions. Frea includes 1-Mbyte of memory on-chip, a 16-bit 800-MHz SPI-4.2 system interface, and a 4-bit 3.125-GHz mate (XAUI) interface that simplifies linking the two chips that are required for a full RPR implementation.